The glass substrate value chain: materials to AI chips
Every chip sits on a substrate — a layer that's carried power and signal between silicon and board for thirty years, almost always built from organic resin (ABF). A glass substrate is the same idea with the core material swapped for glass, and the industry is now piloting that swap because AI accelerator packages have outgrown what resin can hold flat.
This page maps the five stages that turn raw glass into a working chip package, and the companies building each one — with a closer look at the US and Korean side of the chain, since Japanese and European suppliers are already well covered elsewhere.
The structure: 10 redistribution layers on each face of a 2-layer glass core, connected top-to-bottom by copper-filled through-glass vias (TGV). The core swap is small — a few hundred microns of glass instead of resin — but it's what let this particular package span more silicon than an organic substrate could hold flat. Intel presented it as a working sample, not yet a production line.
A sixty-year pattern
Substrate material has shifted three times before. Each shift happened because the previous material hit a physical wall, not because it stopped working entirely.
Based on the individual company timelines detailed on this page — Absolics' 2026 target, Samsung Electro-Mechanics' 2026–27 target, Intel's 2026–2030 range — the industry as a whole appears to be planning pilot qualification through 2026 and volume ramp for 2027–2030. Glass looks like the next entry in that sequence, though the industry's own timelines have slipped before.
Why glass, and why now
Three physical limits of organic (ABF) substrates are driving the move toward glass — and they're the same three limits every candidate material gets judged against.
CTE mismatch. Every heat cycle, a die and its substrate expand at different rates. Silicon moves at roughly 2.3 ppm/°C; ABF moves at around 40 — nearly 20× faster. That gap concentrates stress at the solder joints. It was manageable on small packages; it becomes structural once packages cross 100×100mm, which is where AI accelerators now sit. Glass can be formulated to expand at 3–4 ppm/°C — close enough to silicon that most of the stress disappears.
Flatness. Organic material measurably warps under heat; glass doesn't. Below roughly 100µm bump pitch, ABF's warpage becomes the hard limit on how fine the wiring can go. Glass holds flatness to within a few microns at the same size, which is what lets bump pitch keep shrinking.
Signal loss. Glass's dielectric loss runs several times lower than ABF's. That gap was academic at older data rates; it stops being one as AI accelerator and HBM interfaces push into tens-of-GHz territory, where every dB of loss shows up directly in bandwidth.
The value chain
Glass moves through five stages before it's carrying an AI chip.
Specialty low-CTE, low-dielectric-loss glass, formulated specifically to match silicon's expansion rate rather than borrowed from display or window glass. A small number of glassmakers with decades of precision optical experience supply nearly the whole industry, and glass composition is where the CTE story above actually gets engineered.
Raw glass becomes a substrate here: through-glass vias (TGV) drilled and copper-filled, then built up with redistribution layers. Drilling thousands of holes into a brittle sheet without cracking it — "SeWaRe," from the Japanese for back-crack — is the industry's central yield problem, and no single method solves it cleanly.
Push precision up and speed drops; push speed up and yield breaks down. Drilling tens of thousands of TGVs across a single large panel — without a single crack — is the problem this whole stage is organized around solving.
A microscopic crack that slips past inspection doesn't fail today — it fails after a few hundred thermal cycles, once the package has already shipped. That's what makes this stage the industry's real bottleneck: the tools for TGV formation, plating, dicing, and inspection have to catch what the fabrication stage above can't always avoid producing. Whoever gets crack-free drilling working at volume effectively sets the industry's pace.
Foundries and OSATs that mount dies onto the finished glass substrate and integrate it into a shippable package. Intel showed the first working sample in January 2026, in Tokyo; Samsung is running parallel qualification for its own packaging lines.
The bar here is higher than "it works once." A single unfilled TGV — a void — concentrates stress under thermal cycling and can fail an entire multi-million-dollar package after a few hundred heat cycles. Packaging-stage qualification is really a search for zero voids at volume.
The AI accelerator and HPC designers pulling this transition — the reason glass substrates exist is that their packages outgrew what organic material could hold flat. Based on our research across supply-chain reporting, Intel, AMD, and Amazon are the names that come up most consistently as the first real demand for glass-substrate packages, with 2027–2028 the timeline the supply chain itself is planning around — not 2026, which is still pilot and qualification.
Common questions
What is a glass substrate?
A layer that sits between a computer chip and the circuit board beneath it, built from glass instead of the organic resin (ABF) used in nearly all chips today. It carries power and signal between the two — the same job resin substrates have done for decades.
Why are AI chips driving the switch to glass?
AI accelerator packages have grown so large that resin substrates warp under heat, limiting how big and densely wired a single chip package can be. Glass expands at close to the same rate as silicon, largely eliminating that warping problem.
When will glass substrates reach mass production?
Industry timelines cluster around 2026 for pilot production, with broader volume ramp expected between 2027 and 2030 — though, as with earlier substrate transitions, these dates have already shifted once and could shift again.