TSMC

Who they are

TSMC invented the business model that makes the rest of this value chain possible: the pure-play foundry. Founded in 1987 in Hsinchu, Taiwan, by Morris Chang, TSMC doesn't design a single chip of its own — it manufactures other companies' designs, at a scale and yield no one else has matched. That single decision, to specialize in making chips rather than designing them, is why Nvidia, AMD, Apple, and nearly every serious AI accelerator designer on the planet all end up at the same address.

What they do

TSMC runs the advanced manufacturing nodes — N3 and, increasingly, N2 — that produce the logic dies inside AI GPUs and accelerators. But the part of the business getting all the attention in 2026 isn't the wafer fab, it's what happens after: CoWoS (Chip-on-Wafer-on-Substrate), the advanced packaging process that stacks a finished logic die together with high-bandwidth memory into the single module that actually ships as an AI chip. At TSMC's June 2026 shareholder meeting, CEO C.C. Wei called CoWoS capacity "extremely tight and sold out through 2026." Total CoWoS demand is expected to hit roughly one million wafers in 2026, against about 370,000 in 2024 — nearly a tripling in two years. TSMC has been expanding that capacity at close to 80% a year to keep up, from around 35,000 wafers a month at the end of 2024 toward a targeted 125,000–130,000 by the end of 2026, and it's still not quite enough.

How TSMC makes money

The headline number is chip fabrication revenue, and June 2026 alone set an all-time monthly record at NT$442.68 billion, up 67.9% year-over-year. But the more interesting shift is in the mix: advanced packaging made up about 8% of TSMC's revenue in 2025 and is expected to climb above 10% in 2026, with 10–20% of the company's entire $52–56 billion 2026 capital budget aimed specifically at packaging and testing capacity. TSMC is deliberately shifting capital toward the part of its business that's both the tightest constraint in the industry and, increasingly, one of its highest-margin lines.

The bigger trend

For most of the last two decades, the industry's constraint was transistor scaling — how small a feature TSMC could etch. That problem is essentially solved: N3 and N2 run at high yields. The harder problem now is packaging, and it's created a double chokepoint, since TSMC controls both the logic-die fabrication step and the assembly step that turns that die into a shippable AI chip. Nvidia alone has reportedly secured roughly 60% of TSMC's 2026 CoWoS output, with Nvidia, Broadcom, and AMD together accounting for an estimated 85%-plus of total allocation — which is also why TSMC has started outsourcing some packaging steps to ASE and Amkor just to relieve its own backlog, and why some customers priced out of TSMC capacity have reportedly turned to Samsung Electronics to fill the gap.

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